1. Field of the Invention
The present invention relates to the field of integrated circuits and more specifically to the fabrication of an NPN transistor.
In patent application Ser. No. 08/968,598 filed on Nov. 13, 1997 under attorney docket number S1022/7945, now U.S. Pat. No. 5,953,600 and incorporated herein by reference, a method for fabricating a bipolar transistor compatible with a BICMOS technology (that is, a technology enabling the simultaneous fabrication of bipolar transistors and of complementary MOS transistors) is described.
2. Discussion of the Related Art
An example of NPN transistor obtained by using this technology is shown in FIG. 12A of this patent application, which is reproduced identically in appended FIG. 1.
This NPN transistor is formed in an epitaxial layer 2 which is above a buried layer 3 formed in a P-type silicon substrate (not shown). The transistor is formed in a window made in a thick oxide layer 5. References 21 and 22 designate thin silicon oxide and silicon nitride layers which are not necessary for the description of the bipolar transistor. Region 23 is a P-type doped polysilicon layer called the base polysilicon since the base contact diffusion 32 is formed from this silicon layer. Polysilicon layer 23 is coated with an encapsulation silicon oxide layer 24. A central emitter-base opening is formed in layers 22 and 23 altogether. A thin silicon oxide layer 31 covers the sides of polysilicon layer 23 and the bottom of the opening. In this opening, an N-type high energy implant 30 meant for the forming of a sub-collector region with a selected doping level is performed. The walls of the emitter-base opening are coated with a silicon nitride layer 44. Polysilicon lateral spacers 43 are formed on the sides of the opening. Before the forming of silicon nitride region 44 and of polysilicon spacers 43, an intrinsic base implant 33 is formed. After the spacers have been formed, a highly-doped N-type polysilicon layer 46 from which is formed emitter region 49 is deposited. Polysilicon layer 46 is coated with an encapsulation oxide layer 47. The general structure is coated with an insulating and planarizing layer 51 through which are formed emitter contact openings 55 joining polysilicon layer 46 and base contact openings 56 joining polysilicon layer 23. Further, a collector contact (not shown) is made via an N-type drive-in towards buried layer 3.
Referring to FIG. 1, the emitter-base opening penetrates slightly into the thickness of epitaxial layer 2. This inevitably results from the fabrication process and possible defects in the selectivity of the etching of polysilicon layer 23 with respect to the etching of the substrate silicon.
Actually, the depth of the penetration is not precisely controlled and can for example vary of ±20 nm around a provided value of 30 nm according to slight variations of the fabrication parameters. This results in variable characteristics for the NPN transistor, having a variable distance between the extrinsic base and the intrinsic base and thus having a fluctuating resistance of access to the base. Further, the bottom surface area of the opening—emitter surface area—results from an end of doped polysilicon etching and risks of being of poor quality, which is also prejudicial to the stability of the characteristics of the transistor.